This invention relates to a semiconductor test system for testing semiconductor integrated circuits such as a large scale integrated (LSI) circuit, and more particularly, to a low cost semiconductor test system having an event based tester architecture and is configured exclusively for testing a specific type of memory devices. The event based semiconductor memory test system of the present invention is formed by freely combining a plurality of tester modules having same or different capabilities and an algorithmic pattern generation module for generating an algorithmic test pattern specific to intended memory devices to be tested, thereby establishing a low cost test system. In addition to the tester modules and algorithmic pattern generation module installed in a main frame of the test system, a function module unique to the memory under test can be installed in a test fixture, thereby forming a memory test system which can perform both memory testing and a special process associated with the memory testing.
FIG. 1 is a schematic block diagram showing an example of a semiconductor test system, also called an IC tester, in the conventional technology for testing a semiconductor integrated circuit (xe2x80x9cdevice under testxe2x80x9d or xe2x80x9cDUTxe2x80x9d).
In the example of FIG. 1, a test processor 11 is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor 11, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. A test pattern is produced by the wave formatter 14 with use of the waveform data from the pattern generator 12 and the timing data from the timing generator 13, and the test pattern is supplied to a device under test (DUT) 19 through a driver 15.
In the case where the device under test (DUT) 19 is a memory device, the test pattern applied to the DUT consists of address data, write data, and control data. After writing predetermined data in predetermined addresses of the DUT, the data in the addresses is read to determine whether the data in the memory is the same as the write data.
More particularly, the read out data from the DUT 19 is converted to a logic signal by an analog comparator 16 with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data (write data) from the pattern generator 12 by a logic (pattern) comparator 17. The result of the logic comparison is stored in a failure memory 18 corresponding to the address of the DUT 19 to be used later in a failure analysis stage. In such memory testing, the address data and write data for writing and reading the memory device under test may be a pattern generated by a sequence based on mathematical algorithm. Such a pattern generation algorithm will be selected depending on a physical structure and a test purpose of a particular memory device under test.
The circuit configuration noted above is provided to each test pin of the semiconductor test system. Therefore, since a large scale semiconductor test system has a large number of test pins, such as from 256 test pins to 2048 test pins, and the same number of circuit configurations each being shown in FIG. 1 are incorporated, an actual semiconductor test system becomes a very large system. FIG. 2 shows an example of outer appearance of such a semiconductor test system. The semiconductor test system is basically formed with a main frame 22, a test head 24, and a work station 26.
The work station 26 is a computer provided with, for example, a graphic user interface (GUI) to function as an interface between the test system and a user. Operations of the test system, creation of test programs, and execution of the test programs are conducted through the work station 26. The main frame 22 includes a large number of test pins each having the test processor 11, pattern generator 12, timing generator 13, wave formatter 14 and comparator 17 shown in FIG. 1.
The test head 24 includes a large number of printed circuit boards each having the pin electronics 20 shown in FIG. 1. The driver 15, analog comparator 16 and switches (not shown) for switching the pins of the device under test are provided in the pin electronics 20. The test head 24 has, for example, a cylindrical shape in which the printed circuit boards forming the pin electronics 20 are radially aligned. On an upper surface of the test head 24, a device under test 19 is inserted in a test socket at about the center of a performance board 28.
Between the pin electronics 20 and the performance board 28, there is provided with a pin (test) fixture 27 which is a contact mechanism for transmitting electrical signals therethrough. The pin fixture 27 includes a large number of contactors such as pogo-pins for electrically connecting the pin electronics 20 and the performance board 28. As noted above, the device under test 19 receives a test pattern from the pin electronics and produces a response output signal.
In the conventional semiconductor test system, for producing a test pattern to be applied to a device under test, the test data which is described by, what is called a cycle based format, has been used. In the cycle based format, each variable in the test pattern is defined relative to each test cycle (tester rate) of the semiconductor test system. More specifically, test cycle (tester rate) descriptions, waveform (kinds of waveform, edge timings) descriptions, and vector descriptions in the test data specify the test pattern in a particular test cycle.
In the design stage of the device under test, under a computer aided design (CAD) environment, the resultant design data is evaluated by a logic simulation process through a test bench. However, the design evaluation data thus obtained through the test bench is described in an event based format. In the event based format, each change point (event) in the particular test pattern, such as from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d or from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, is described with reference to a time passage. The time passage is defined by, for example, an absolute time length from a predetermined reference point or a relative time length between two adjacent events.
The inventor of this invention has disclosed the comparison between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format in the U.S. patent application Ser. No. 09/340,371. The inventor of this invention has also proposed an event based test system as a new concept test system. The detailed description on the structure and operation of the event based test system is given in the U.S. patent application Ser. No. 09/406,300, now U.S. Pat. No, 6,532,561 owned by the same assignee of this invention.
As described in the foregoing, in the semiconductor test system, a large number of printed circuit boards and the like which is equal to or greater than the number of the test pins are provided, resulting in a very large system as a whole. In the conventional semiconductor test system, the printed circuit boards and the like are identical to one another.
For example, in a high speed and high resolution semiconductor test system, such as a test rate of 500 MHz and timing accuracy of 80 picosecond, the printed circuit boards for all the test pins have the same high capabilities each being able to satisfy this test rate and timing accuracy. Thus, the conventional semiconductor test system inevitably becomes a very high cost system. Further, since the identical circuit structure is used in each test pin, the test system can conduct only limited types of test.
For example, in a semiconductor test system for testing memory devices, an algorithmic pattern generator (ALPG) for generating algorithmic test pattern to be applied to a memory under test is so configured that it can generate any types of pattern for anticipated memory devices. However, an algorithmic pattern most suitable for memory devices differs depending on types of memory device. Therefore, in the case where the types of memory to be tested are limited, such an algorithmic pattern generator results in including functions which will never be used in the test, which increases the overall cost.
Further, in the conventional semiconductor memory test system, the algorithmic pattern generator (ALPG) generates an algorithmic test pattern that is directly applied to a memory device under test. Under this situation, the test pattern must be generated at speed, i.e., the speed of actual operation speed of the memory under test. Thus, the algorithmic pattern generator (ALPG) must be designed so that it can generate the algorithmic test pattern at high speed, resulting in further increase in the cost.
Further, the algorithmic pattern generator (ALPG) used in the conventional semiconductor memory test system is so structured that the data is extracted from the instruction memory formed in the pattern generator based on the program. Thus, the algorithmic pattern generator requires times to access the instruction memory, which makes it difficult to generate the algorithmic test pattern at high speed. For generating the algorithmic test pattern at high speed, high speed memory devices must be used, which increases the cost of the pattern generator.
One of the reasons that the conventional semiconductor test system installs the identical circuit configuration in all of the test pins as noted above, and as a result, not able to conduct two or more different kinds of test at the same time by having different circuit configuration, is that the test system is configured to generate the test pattern by using the cycle based test data. In producing the test pattern using the cycle based concept, the software and hardware tend to be complicated, thus, it is practically impossible to include different circuit configurations and associated software in the test system which would make the test system even more complicated. Further, because of these reasons, it is necessary for the algorithmic pattern generator (ALPG) for memory device testing to achieve a high speed operation and to generate test patterns for all types of memory device.
To explain the above noted reasons more clearly, brief comparison is made between the test pattern formation using the test data in the cycle based format and the test pattern formation using the test data in the event based format with reference to waveforms shown in FIG. 3. The more detailed comparison is disclosed in the above noted U.S. patent applications owned by the same assignee of this invention.
The example of FIG. 3 shows the case where a test pattern is created based on the data resulted from the logic simulation conducted in the design stage of the large scale integrated circuit (LSI). The resultant data is stored in a dump file 37. The output of the dump file 37 is configured with data in the event based format showing the changes in the input and output of the designed LSI device and having descriptions 38 shown in the lower right of FIG. 3 for expressing, for example, the waveforms 31 such as VCD (Value Change Dump) of Verilog.
In this example, it is assumed that test patterns such as shown by the waveforms 31 are to be formed by using such descriptions above. The waveforms 31 illustrate test patterns to be generated at pins (tester pins or test channels) Sa and Sb, respectively. The event data describing the waveforms is formed of set edges San, Sbn and their timings (for example, time lengths from a reference point), and reset edges Ran, Rbn and their timings.
For producing a test pattern to be used in the conventional semiconductor test system based on the cycle based concept, the test data must be divided into test cycles (tester rate), waveforms (types of waveforms, and their edge timings), and vectors. An example of such descriptions is shown in the center and left of FIG. 3. In the cycle based test pattern, as shown by waveforms 33 in the left part of FIG. 3, a test pattern is divided into each test cycle (TS1, TS2 and TS3) to define the waveforms and timings (delay times) for each test cycle.
An example of data descriptions for such waveforms, timings and test cycles is shown in timing data (test plan) 36. An example of logic xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d or xe2x80x9cZxe2x80x9d of the waveforms is shown in vector data (pattern data) 35. For example, in the timing data 36, the test cycle is described by xe2x80x9cratexe2x80x9d to define time intervals between test cycles, and the waveform is described by RZ (return to zero), NRZ (non-return to zero) and XOR (exclusive OR). Further, the timing of each waveform is defined by a delay time from a predetermined edge of the corresponding test cycle.
As in the foregoing, because the conventional semiconductor test system produces a test pattern under the cycle based procedure, the hardware structures in the pattern generator, timing generator, and wave formatter tend to be complicated, and accordingly, the software (test data) to be used in such hardware becomes complicated as well. Further, since all of the test pins (such as Sa and Sb in the above example) are defined by the common test cycle, it is not possible to generate test patterns of different cycles among the test pins at the same time.
Therefore, in the conventional semiconductor test system, the same circuit configurations are used in all of the test pins, and it is not possible to incorporate printed circuit boards of different circuit structures therein. As a consequence, it is not possible to perform different test such as the analog block test and the digital block test at the same time in a parallel fashion. Moreover, for example, a high speed type test system also needs to include a low speed hardware configuration (such as high voltage and large amplitude generation circuit and a driver inhibit circuit, etc.), thus, the high speed performance cannot be fully improved in such a test system.
In contrast, for producing a test pattern by using the event based method, it is only necessary to read set/reset data and associated timing data stored in an event memory, requiring very simple hardware and software structures. Further, each test pin can operate independently as to whether there is any event therein rather than the test cycle and various types of associated data, thus, test patterns of different functions and frequency ranges can be generated at the same time.
As noted in the foregoing, the inventor of this invention has proposed the event based semiconductor test system. In the event based test system, since the hardware and software involved are very simple in the structure and contents, it is possible to formulate an overall test system having different hardware and software among the test pins therein. Moreover, since each test pin can operate independently from the other, two or more tests which are different in functions and frequency ranges from one another can be carried out in a parallel fashion at the same time. Since an event based test system has high flexibility, it is possible to test a memory block and a logic block in the device under test at the same time. Further, it is possible to establish a low cost event based memory test system which is specific to a type of memory devices to be tested and to a test purpose.
Therefore, it is an object of the present invention to provide a semiconductor test system which is dedicated to a specific application by having tester modules of different capabilities corresponding to test pins and a function module to be used for the specific application in a test fixture.
It is another object of the present invention to provide a semiconductor test system which is capable of testing different functional cores in a system IC (system-on-chip) having such as a processor core and a memory core in parallel at the same time by having an arbitrary combination of logic tester modules and memory tester modules corresponding to test pins.
It is a further object of the present invention to provide a simple and low cost semiconductor memory test system which can be configured depending on a type of memory device under test or a test purpose by incorporating tester modules of different capabilities corresponding to test pins and an algorithmic pattern generator module designed for a specific application.
It is a further object of the present invention to provide a simple and low cost semiconductor memory test system which can be configured depending on a type of memory device under test or a test purpose by incorporating tester modules of different capabilities corresponding to test pins, an algorithmic pattern generator module designed for a specific application, and a function module having a specific relationship with the memory device under test.
It is a further object of the present invention to provide a simple and low cost semiconductor memory test system which can be configured depending on a type of memory device under test or a test purpose by incorporating tester modules of different capabilities corresponding to test pins and an algorithmic pattern generator module configured by a programmable logic device such as a field programmable gate array (FPGA).
It is a further object of the present invention to provide a semiconductor memory test system having tester modules of different capabilities corresponding to test pins wherein interface specification between the test system main frame and the tester modules is standardized for freely accommodating tester modules of different pin counts and performances in the main frame.
It is a further object of the present invention to provide a semiconductor test system which can test a semiconductor device under test at low cost and further enhance its ability to meet the future needs.
The semiconductor memory test system of the present invention includes two or more tester modules whose performances are different from one another, an algorithmic pattern generator (ALPG) module for generating an algorithmic pattern specific to a memory device under test, a test system main frame for installing a combination of two or more tester modules and ALPG module therein, a test fixture provided on the test system main frame for electrically connecting the tester modules and a device under test, a function module provided in the test fixture for performing a function specific to the memory device under test and associated with the test result of the memory device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules and the ALPG module through a tester bus.
The semiconductor memory test system of the present invention utilizes the ALPG module which is designed to generate only the algorithmic pattern necessary for the specific memory device or test purpose. Accordingly, in the present invention, various combinations of tester module and ALPG module can be selectively formed, thereby establishing a low cost test system which is specific to an intended memory device under test.
In the semiconductor memory test system of the present invention, the function module is provided in the test fixture which electrically connects the tester module and the device under test, and such a test fixture is replaced with other test fixture based on the device to be tested or intended purpose. The tester module consists of a plurality of tester boards where, under the control of the host computer, each tester board provides a test pattern to a corresponding device pin and evaluates a response output of the device under test.
In the event based memory test system of the present invention, the function module exclusively designed for specific application is installed in the test fixture (pin fixture). Thus, the test system can achieve the function which is specific to the memory device under test as well as the function which is associated with the test result, such as the repair of the memory cells in the memory device under test. As a consequence, by replacing the test fixture depending on the memory device under test, a semiconductor memory test system of simple structure and low cost can be achieved.
In the semiconductor memory test system of the present invention, each test pin can operate independently from the other. Thus, two or more test pin groups can perform the test for different devices or different blocks in the device in parallel at the same time. Accordingly, a plurality of different functional blocks (cores) in a system-on-chip IC, such as a logic core and a memory core, can be tested in parallel at the same time.
Since the semiconductor test system of the present invention has a modular structure, a desired test system can be formed freely depending on the kind of devices to be tested and the purpose of the test. Further, the hardware of the event based test system can be dramatically reduced while the software for the test system can be dramatically simplified. Accordingly, the tester modules of different capabilities and performances can be installed together in the same test system. Furthermore, an overall physical size of the event based test system can be considerably reduced, resulting in further cost reduction, floor space reduction and associated cost savings.